A typical prior art static random access memory (SRAM) scheme for sensing the logic state of a memory cell is shown in the schematic drawing of FIG. 1.
Loads 2 and 4 for bit lines BL and BL.sub.-- respectively, each comprise a n-channel transistor including its gate tied to its source. Bit line pre-charge circuitry comprises n-channel depletion mode transistors 6 and 8 connected to p-channel transistor 10 which is connected to and across bit lines BL and BL.sub.--. Bit line capacitances associated with bit lines BL and BL.sub.-- are represented by capacitors 12 and 14 respectively between ground and the associated bit line. N-channel bit line transistors 16 and 18 connect bit lines BL and BL.sub.-- respectively to sense amplifier (hereinafter also referred to as sense amp) 20 which comprises two cross coupled inverters 22 and 24 each comprising a p-channel transistor including a common drain and gate connection with an n-channel transistor. Inverter 22's p-channel transistor is labeled 25 while its n-channel transistor is labeled 26. Inverter 24's p-channel transistor is labeled 28 while its n-channel transistor is labeled 30. The common drain connection at node A of inverter 22 is connected to the common gate B connection of inverter 24 and in like manner, the common drain connection at node C of inverter 24 is connected to the common gate connection D of inverter 22. Capacitors 34 and 36 represent sense amp capacitance at nodes A and C respectively. Sense amp latch transistor SAL comprises a n-channel transistor with its drain connected to the sources of transistors 26 and 30. Sense amp pre-charge circuitry 32 is connected to bit lines BL and BL.sub.--. Memory cells comprising cross-coupled CMOS inverters 3 lie between bit lines BL and BL.sub.-- and are connected to the same through pass transistors (PT). The pass transistors are activated by voltages placed on the gates which are connected to an associated word line (WL.sub.n, n=12 . . . ) in the SRAM. The foregoing prior art SRAM is built on bulk semiconductor material such as bulk silicon.
The operation of the prior art sensing scheme of FIG. 1 is as follows. Bit lines BL and BL.sub.-- are pre-charged by pre-charge circuitry comprising transistors 6, 8 and 10 when turned on by driving their gates to logic low. Under this condition, after a period of time, the voltages on bit lines BL and BL.sub.13 are balanced through transistor 10 in response to the operation of transistors 6 and 8. Sense amp 20 is then pre-charged by sense amp pre-charge circuitry. Word line WL of a memory cell in the column of cells illustrated is enabled to select a desired memory cell. Sense amp 20 is isolated from bit lines BL and BL.sub.-- by pass transistors 16 and 18, since a single sense amp generally serves a block or a number of columns of memory (although for purpose of clarity of explanation, only one column of memory is shown in FIG. 1--Note however, that by having a structure short of a one-to-one correspondence between the columns of memory cells and the sense amps, as is generally found in the prior art, certain computer architecture schemes for accessing memory cells do not achieve their optimum access speed potential). Next, sense amp 20 is connected to bit lines BL and BL.sub.-- by turning on transistors 16 and 18 (placing a logic high voltage at their gates). When transistor SAL is turned on sense amp 20 latches the logic states of bit lines BL and BL.sub.--. Thus, the logic state of the selected memory can now be sensed by circuitry which is not shown. Pass transistors 16 and 20 are then turned off in order to prepare for the sensing of the logic state of a memory cell from perhaps another column of memory cells.
The sensing scheme illustrated in FIG. 1 depends on symmetrical construction and operation of the elements in the scheme on the right side with the left side. Errors in sensing the correct logic state, arising from asymmetries in the sensing scheme can occur in the prior art sensing scheme illustrated in FIG. 1.
One of these asymmetries in the scheme is unequal capacitance existing at nodes A and C. For instance, if the capacitance at sense amp capacitor 36 is large compared with that of capacitor 334, and bit line BL is high relative to bit line BL.sub.--, when sense amp 20 is latched, bit line BL will pull down in voltage faster than BL.sub.-- due to the smaller capacitance of capacitor 34, possibly causing the wrong memory cell state to be sensed.
A second asymmetry can arise through the improper pre-charging of sense amp 20 and improper pre-charging of bit lines BL and BL.sub.--. For instance node A of sense amp 20 may be inadequately pre-charged with respect to node C or bit line BL.sub.-- may be re-charged over sufficiently with respect to bit line BL. In any such case, by the time transistor SAL is turned on, an incorrect differential voltage may exist at nodes A and C of sense amp 20 or bit lines BL and BL.sub.-- and as a result two possible improper pre-charge operations arise, namely pre-charging of the bit lines and pre-charging of the sense amp. Thus, sense amp 20 will latch an improper memory cell logic state.
A third asymmetry leading to incorrect sensing arises from non-symmetrical transistor sizes and/or doping. An example of this, as it relates to the sense amp, shall be explained with reference to FIG. 2 which is a schematic drawing of a sense amplifier wherein applicable reference numbers from FIG. 1 have been carried forward. As shown, a threshold voltage Vt is indicated for each transistor as well as a gate voltage, Vg, for n-channel transistors 26 and 30. Asymmetry exists in the transistors 26 and 30 as indicated by their different threshold voltages which in an ideal sense amp should be the same. The source voltage, Vs, for transistors 26 and 30 is 3.5 volts (3.5V) as shown. In order to get understanding of the degree to which the n-channel transistors 26 and 30 are turned on or rather to see the effects of the asymmetry, the difference between the gate to source voltage, Vgs, threshold voltage is calculated for each transistor.
For transistor 26.fwdarw.Vgs-Vt=(4.8-3.5)-0.8=0.5V.
For transistor 30.fwdarw.Vgs-Vt=(5-3.5)-1.2=0.3V.
From the above, it is obvious that transistor 26, considering all else equal, is turned on more strongly than transistor 30. For the case where bit line BL is higher in voltage than bit line BL.sub.-- of FIG. 1, this particular asymmetry may result in the sense amp latching the wrong logic state.
It is therefore necessary for the differential voltage between the bit lines to be larger than the voltage differences caused by any asymmetries affecting the latch. Although the foregoing asymmetry problems have been described separately, they can exist simultaneously and therefore possibly compound the severity of the effects of the asymmetry. A need therefore exists to minimize sources of asymmetry and also the amount of asymmetry in the construction and operation of an SRAM sensing scheme.